1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a semiconductor integrated circuit device. More particularly, the invention relates to a memory cell and circuit technology that achieve speed enhancement in view of process miniaturization of a mask ROM (mask programmable ROM), a type of ROM that can be programmed using a mask.
2. Description of the Prior Art
A semiconductor memory device of the prior art is disclosed, for example, in Japanese Unexamined Patent Publication No. H06-176592. In the cited patent publication, the configuration of a contact mask programmable ROM is described in paragraphs 0002 to 0006 on page 2 with reference to FIG. 2.
FIG. 7 is a circuit diagram showing the configuration of the such a contact mask programmable ROM. The contact mask programmable ROM is a ROM that stores data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d depending on whether the drain of a memory cell transistor is connected or not connected to its associated bit line. This mask ROM can be programmed using a mask.
The semiconductor memory device of the prior art comprises, as shown in FIG. 7, a column decoder 2, a buffer 3, a precharging transistor 4, a memory cell array 7, and an off-leakage charge replenishing transistor 8.
The column decoder 2 comprises N-type MOS transistors QCj (j=1 to n). The drains of the N-type MOS transistors QCj are connected in common, while their sources are connected to respective bit lines BLj (j=1 to n), and their gates to respective column select signal lines CLj (j=1 to n).
The input end of the buffer 3 is connected to the common drain of the N-type MOS transistors QCj (j=1 to n) forming the column decoder 2, and its output end is connected to a data output terminal SOUT.
The precharging transistor 4 is constructed from a P-type MOS transistor. The gate of the precharging transistor 4 is connected to a precharge control signal line PCLK1, the source is connected to a power supply terminal having a power supply potential, and the drain is connected to the common drain of the N-type MOS transistors QCj (j=1 to n) forming the column decoder 2.
The memory cell array 7 is a matrix array of memory cells M(i, j) (i=1 to m, j=1 to n) each constructed from an N-type MOS transistor. The gates of the memory cells M(i, j) having the same value of i, that is, arranged in the same row, are connected in common to the same word line WLi (i=1 to m). The sources of these memory cells M(i, j) are connected to a ground potential line GL. The drain of each memory cell is connected to its associated bit line BLj (j=1 to n) when the data stored therein is xe2x80x9c1xe2x80x9d, but is held in a floating state when the stored data is xe2x80x9c0xe2x80x9d.
The off-leakage charge replenishing transistor 8 is constructed from a P-type MOS transistor. The gate of the off-leakage charge replenishing transistor 8 is connected to the output end of the buffer 3, the source is connected to the power supply terminal, and the drain is connected to the common drain of the N-type MOS transistors QCj (j=1 to n) forming the column decoder 2. The ON current of the off-leakage charge replenishing transistor 8 is chosen to be smaller than the ON current of the memory cells M(i, j) (i=1 to m, i=1 to n).
The operation for reading data from the memory cell M(1, 1) in the thus constructed semiconductor memory device will be described with reference to the timing diagram of FIG. 8.
Of the column select signal lines CLj (j=1 to n), the column select signal line CL1 is driven to the xe2x80x9cHxe2x80x9d level, while holding the other column select signal lines CL2 to CLn at the xe2x80x9cLxe2x80x9d level; as a result, of the N-type MOS transistors QCj (j=1 to n) forming the column decoder 2, the N-type MOS transistor QC1 is ON, and the other N-type MOS transistors QC2 to QCn are OFF.
Next, the precharge control signal line PCLK1 is driven to the xe2x80x9cLxe2x80x9d level for a period Tp, thus causing the precharging transistor 4 to turn on for the duration of the prescribed period Tp. As a result, the bit line BL1 is charged to the xe2x80x9cHxe2x80x9d level.
After the bit line BL1 has been charged to the xe2x80x9cHxe2x80x9d level, of the word lines WLi (i=1 to m) the word line WL1 is raised from the xe2x80x9cLxe2x80x9d level to the xe2x80x9cHxe2x80x9d level, while holding the other word lines WL2 to WLm at the xe2x80x9cLxe2x80x9d level.
Here, when the drain of the memory cell M(1, 1) is connected to the bit line BL1, the charge stored on the bit line BL1 and the charge supplied from the off-leakage charge replenishing transistor 8 are discharged through the memory cell M(1, 1), and the bit line BL1 goes to the xe2x80x9cLxe2x80x9d level, so that the input to the buffer 3 is also at the xe2x80x9cLxe2x80x9d level. As a result, after a delay of time Tac3, xe2x80x9cHxe2x80x9d is read out at the data output terminal SOUT, and the off-leakage charge replenishing transistor 8 turns off (indicated by dashed lines in FIG. 8).
On the other hand, when the drain of the memory cell M(1, 1) is not connected to the bit line BL1, the charge stored on the bit line BL1 is not discharged through the memory cell M(1, 1), the bit line BL1 is held at the xe2x80x9cHxe2x80x9d level, so that the input to the buffer 3 is also at the xe2x80x9cHxe2x80x9d level. As a result, xe2x80x9cLxe2x80x9d is read out at the data output terminal SOUT, and the off-leakage charge replenishing transistor 8 turns on. The charge being discharged due to the off-leakage currents of the other memory cells (i, 1) (i=2 to m) whose drains are connected to the bit line BL1 is replenished by the off-leakage charge replenishing transistor 8 turning on. Accordingly, the bit line BL1 is held at xe2x80x9cHxe2x80x9d, and the data output terminal SOUT can thus continue to read out xe2x80x9cLxe2x80x9d (indicated by solid lines in FIG. 8).
In the prior art, the semiconductor memory device has the following problem. In the semiconductor memory device, the drains of a plurality of memory cells whose sources are grounded are connected to the same bit line, depending on the values of their stored data. As a result, a steady state current occurs on the bit line due to the off leakages of the plurality of memory cells.
Therefore, when reading data from a memory cell whose drain is not connected to the bit line, the charge being discharged as a result of the steady state current occurring due to the off leakages of the memory cells must be replenished in order to keep the bit line at the xe2x80x9cHxe2x80x9d level; the off-leakage charge replenishing transistor 8 is provided to supply the necessary charge to the bit line.
In recent years, with the rapid advance of miniaturization, the off-leakage current of a transistor forming a memory cell has been increasing at an extraordinarily rapid pace; as a result, the ON current of the off-leakage charge replenishing transistor for supplying charge to the bit line to make up for the charge being discharged as a result of the steady state current occurring due to the off leakages must also be increased.
For a memory cell whose drain is connected to the bit line, this in turn means that, when reading the data stored in the cell by discharging the bit line and thereby driving the bit line to the xe2x80x9cLxe2x80x9d level, it takes a long time for the charge supplied from the off-leakage charge replenishing transistor to be discharged through the ON current of the memory cell. The resulting problem is that the data cannot be read out at high speed.
The present invention has been devised to solve the prior art problem of the semiconductor memory device described above, and an object of the invention is to provide a semiconductor memory device that can hold the bit line at the xe2x80x9cHxe2x80x9d level without needing the off-leakage charge replenishing transistor, and can accomplish readout at high speed.
A semiconductor memory device according to the present invention comprises: a plurality of memory cell transistors arranged in a matrix form; a plurality of bit lines and a plurality of word lines to which drains and gates of the memory cell transistors are respectively connected; and a high-potential source line and a low-potential source line to which sources of the memory cell transistors are selectively connected. Here, the source of each of the memory cell transistors is connected by mask programming to either said high-potential source line or said low-potential source line, depending on data to be held for said each memory cell transistor.
According to the above configuration, in the case of stored data that requires its associated bit line be kept at a high potential (xe2x80x9cHxe2x80x9d level), the charge being discharged due to the off-leakage of deselected memory cell transistors can be replenished by connecting the source of the selected memory cell transistor to the high-potential source line. This eliminates the need for the off-leakage charge replenishing transistor provided in the prior art to replenish the charge being discharged due to the off-leakage of the deselected memory cell transistors. Since the charge is not supplied to the bit line, when driving the bit line to a low potential (xe2x80x9cLxe2x80x9d level) by discharging it, stored data can be read out at high speed by connecting the source of the selected memory cell to the low-potential source line.
Preferably, in the semiconductor memory device of the present invention, a plurality of high-potential source lines and a plurality of low-potential source lines are formed parallel to the plurality of bit lines.
Further, in the semiconductor memory device of the present invention, it is preferable that the high-potential source line and the low-potential source line are respectively formed in different wiring layers.
According to the above configuration, the high-potential source line and the low-potential source line can be formed one on top of the other, which serves to reduce the memory cell area.
The semiconductor memory device of the present invention may further include: a decoder for selecting one bit line from among the plurality of bit lines; and a level shifter for supplying a potential intermediate between a high potential and a low potential to the bit line selected by the decoder.
According to the above configuration, since the bit line potential need only transition from the intermediate potential to the high potential (xe2x80x9cHxe2x80x9d level) or the low potential (xe2x80x9cLxe2x80x9d level), readout can be accomplished at higher speed than in the configuration where neither the decoder nor the level shifter is provided.
In the semiconductor memory device further provided with the decoder and the level shifter described above, it is also preferable that the high-potential source line and the low-potential source line are respectively formed in different wiring layers.
According to the above configuration, the high-potential source line and the low-potential source line can be formed one on top of the other, which serves to reduce the memory cell area.
As described above, according to the present invention, the high-potential (xe2x80x9cHxe2x80x9d level) and low-potential (xe2x80x9cLxe2x80x9d level) source lines are provided, and data writing is performed by connecting the source of the memory cell transistor to one or the other of the source lines that corresponds to the stored data; as a result, without needing the off-leakage charge replenishing transistor formerly required to replenish the charge being discharging due to the steady state current occurring as a result of off leakage, the semiconductor memory device of the invention can easily accomplish the holding of the bit line at the xe2x80x9cHxe2x80x9d level and the high-speed readout of the stored data.